Standards developed by the Motion Picture Experts' Group (MPEG), such as MPEG-2, provide techniques of compressing digital video for storage and transmission. The MPEG-2 standard uses techniques that take advantage of both spatial and temporal redundancies in video frames to reduce the amount of memory and bandwidth required to store and transmit the video frames.
Spatial compression relies on similarities between adjacent pixels in plain areas of a picture and on dominant spatial frequencies in areas of patterning. Temporal redundancies are exploited by interceding or transmitting only the differences between pictures. The MPEG-2 standard uses three different types of pictures. I-pictures are intra-coded pictures hat need no additional information for decoding. P-pictures are forward predicted from an earlier picture, which can be either an I-picture, or another P-picture. B-pictures are bidirectionally predicted from earlier and/or later I or P-pictures.
The use of B-pictures present unique challenges for decoding pictures. B-pictures are data dependent on both past prediction pictures and future prediction pictures. As a result, the future prediction picture are required to be decoded prior to decoding the B-pictures. However, the B-pictures are displayed prior to the future prediction picture.
The foregoing is resolved by the use of frame buffers. The frame buffers store decoded pictures. Typically, three frame buffers are used for decoding and displaying the pictures. One of the frame buffers stores the decoded past prediction picture, and another one of the frame buffers stores the decoded future prediction picture. The third frame buffer is used to decode B-pictures. Data dependent pictures use the decoded past prediction picture and/or the future prediction picture for decoding.
The pictures stored in the frame buffers are displayed according to the presentation order. The B-pictures is displayed almost immediately after the B-picture is decoded and written to the frame buffer. The I-pictures and P-pictures are usually displayed after a time delay determined by the number of pictures that are data dependent on the I-pictures and P-pictures.
Standard Definition Television (SDTV) is a television standard for providing digital video. A typical SDTV frame has a 720×480 resolution. In the 4:2:0 type picture, there are one set of color pixels (Cr and Cb) for every four luminance pixels. The luminance pixels and each color pixel comprise one byte of data. Accordingly, 518,400 bytes are required to store an SDTV frame with 720×480 resolution. Approximately 1.55 MB are required to store three SDTV frames. High Definition Television (HDTV) is a scheme for providing high resolution video. One HDTV standard defines approximately frames with 1280×720 resolution. Such frames comprise 1.382 MB of data. Three such frames comprise approximately 4.146 MB of data. Another HDTV standard defines frames with 1920×1088 resolution. Such frames comprise approximately 3.133 MB of data. Three such frames comprise 9.4 MB of data.
Typical MPEG decoding circuits are implemented as a board level product with a combination of processors, firmware, dedicated hardware, and memory. The frame buffers are usually implemented in an off-the-shelf SD-RAM memory module or chip. Off-the-shelf SD-RAM memory modules or chips are sold in standard sizes which are typically in exponential powers of two, such as 1, 2, 4, 8, 16, 32, 64 MB, etc.
As noted above, three SDTV frames comprise 1.57 MB of data. A 2 MB chip is generally used for implementing the SDTV frame buffers. Also noted above, three 1280×720 HDTV frames comprise 4.146 MB of data. Generally, an 8 MB chip is used for implementing the 1280×720 HDTV frames. Also noted above, three 1920×1088 HDTV frames comprise approximately 9.4 MB of data. Generally, a 16 MB chip is used for implementing the 1920×1088 HDTV frame buffers.
The foregoing results in considerable memory wastage and also increases costs. Another approach is to place two frames on one chip, and a third frame on a smaller chip. The foregoing reduces memory wastage. However, the reduced memory wastage is offset by increased design complexity and the increased real estate requirements of fusing an additional chip. Furthermore, memory wastage is still considerable.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application.